This invention is in the field of digital data transmission and reception. More particularly, it comprises a digital data receiver having a fast data synchronizing latch, a fast clock gate, and improved delay line.
Serial data applications such as disk drives, local area networks (`LANs`) and optical data storage transmit and receive data in the form of discrete data pulses. To simplify the transmission requirements, the data and related clock information are combined and transmitted over a single serial channel by using an appropriate form of data encoding. The unit which receives this combined data/clock digital signal incorporates the circuits necessary to recover the clock signal and data.
A known clock/data receiver circuit is shown in FIG. 1. In receiver 10, clock recovery circuit 11 typically comprises a phase-locked loop (`PLL`) which generates a local clock, the rising edges of the local clock being coincident with the rising edges of the incoming data pulses, received from Peak/Edge detector 14. If 50% symmetry is maintained in the recovered clock waveform, the falling edges of the clock are exactly coincident with the data bit cell boundaries. The clock falling edges are then used by decision circuit 12 to re-clock the data.
Decision circuit 12 is subject to several design constraints. At the boundaries of the data cell windows for the receiver, the region where the state of the data cannot be precisely determined (also called `metastability region`) must be minimized to reduce the possibility of data errors. The decision circuit must also recover quickly after the transmission of each data bit to allow for maximum data transfer capability (also known as high data frequency). Finally, the recovered data pulse which leaves the decision circuit and which is sent to controller 13 should be equal in time to the period of the recovered clock. This maximizes the available set-up and hold times for subsequent decoding and deserialization circuitry.
FIGS. 2 and 4 illustrate known decision circuits. The decision circuit of FIG. 2 is comprised of a first flip-flop 17 and a second flip-flop 15. Although the decision circuit of FIG. 2 produces an output pulse of the appropriate width (duration), it cannot tolerate the reception of repetitive data pulses which occur at or above the clock frequency. In the circuit shown in FIG. 2, the pulses must be spaced by one empty data bit cell to allow flip-flop 15's Q output to fall and release flip-flop 17. Although this is acceptable for many types of channel encoding schemes, it is inappropriate for those applications which transmit data at the clock frequency. Also, even when used in applications where data bits are spaced by at least one empty bit cell, the circuit may yield errors if the data is "jittery" due to random noise which pushes the data bits closer together than the circuit can tolerate.
As shown in FIG. 3, only data bits which are widely separated in time, such as bits 16 and 18, can be properly detected by the circuit shown in FIG. 2. Any bunching of data results in loss of data. Although data bits 16, 18, and 20 are properly detected and result in SD1 bits 26, 28 and 30, data bits 19 and 21 are undetected.
The circuit shown in FIG. 4 employs three flip-flops, numbered 41, 43, and 45 and a backlash clear method. As in the circuit of FIG. 2, flip-flop 41 is used as a bit trap--its output Q is set to a logical 1 whenever a data bit arrives (e.g., bit 51). The next arriving clock pulse edge at T.sub.n sets flip-flop 43's Q output to a logic 1, which in turn clears all three flip-flops (`backlash clear`). Clearing flip-flop 45 initiates the SD2 output pulse at flip-flop 45's Q output (e.g., bit 62). The clear pulse generated by flip-flop 43 is quite short, which allows flip-flop 41 to receive new data one full clock period sooner than flip-flop 17 could in FIG. 2. At time T.sub.n+1, the incoming clock pulse's edge re-clocks flip-flop 45 into the low state, ending the synchronized data output pulse SD2. Flip-flop 41 cannot accept new data until approximately 2 gate delays (the propagation delay of flip-flop 43 and the clear-release time of flip-flop 41) following the rising clock edge at time T.sub.n. Consequently, from the time a bit in data cell N first clocks flip-flop 41 until flip-flop 41 is cleared or released, a "blind spot" encroaches into the next bit cell. As transfer frequency is increased and data bit size decreases, this blind region can extend over significant portions of the next N+1 data cell. This truncation of cell N+1 reduces high frequency data transmission and increases the error rate in so-called jittery data. The blind spot can be even wider as the clear pulse is extended, as is often necessary to insure proper operation. Also, the resulting SD2 output pulse is less than the desired width of one clock period as its leading edge is delayed more than its trailing edge.
As shown in FIG. 5, input data pulses 51, 53, 55 and 57 are all correctly detected and transmitted as SD2 output pulses 61, 63, 65 and 67, respectively. However, input pulse 59 has no corresponding output pulse, as the interval between delay pulse 57 and 59 is less than the two gate delay requisite to clear flip-flop 41.
As shown in FIG. 6, clock recovery circuit 11 shown in FIG. 1 is further comprised of a half cell delay 81, a positive-edge triggered phase/frequency comparator 83, clock gate 87 and VCO 85. In known clock recovery circuits, PLLs are often used for timing extraction. The output of the PLL comprises the recovered clock, which is in digital form. The output from the PLL is fed back to the negative input of a phase/frequency detector. Typically, the phase/frequency detector has a full frequency discrimination capability, which can force the local voltage/current controlled oscillator (VCO/ICO) toward the input data frequency regardless of the magnitude of the frequency difference. As the channel data is pseudo-random and often has no component t the actual clock frequency, unqualified feedback of the VCO would result i a widely wandering, unusable VCO frequency. To avoid this, the VCO feedback signal is first qualified by the arrival of an input data pulse on a one-to-one basis prior to being allowed into the negative input of the phase/frequency comparator. This qualifier circuit is referred to herein as clock gate 87. Like the first data synchronizing latch, the clock gate establishes a window about the average input data leading edge. If a data pulse arrives within any given window, i.e., between active clock edges, the next occurring clock edge is transmitted to the phase/frequency comparator circuit. An anticipator delay of one-half the VCO period is used to set and center this gating window.
Like the decision circuit, the clock gate should have a very small region of metastability at the window boundaries for minimum decision loss, a rapid recovery from transmission of each bit for maximum transfer rate capability (high data frequency) and an adequate gated clock output pulse width for subsequent circuitry.
The circuit shown in FIG. 2 can be used as a clock gate. It has the same drawbacks when used as a clock gate as it did when used as a data latch, which limits its usefulness for high transfer rates and certain code types. A modification of this circuit, shown in FIG. 7, creates a backlash arrangement similar to that shown in FIG. 4. Unlike that circuit, it does not have a third flip-flop, which was used therein to reshape the output pulse to about the width of one clock cycle. Herein, the output GC2 pulse width is set by the self-clearing time of flip-flop 103. This pulse width may be inadequate for downstream circuitry and may have to be widened by the inclusion of additional delay gates in the clear path. Unfortunately, this also extends the "blind spot" width, discussed previously relative to FIGS. 2 and 4.
FIG. 8 illustrates a sample input, clock and output waveform when the circuit of FIG. 2 is used as a clock gate. Note how data pulses one clock period or less apart (pulses 91 and 93, 97 and 99) result in the second clock pulse being lost. As shown in FIG. 9, the circuit shown in FIG. 7 performs slightly better, as it detects pulses 1 clock cycle (see pulses 71 and 75, whose output are pulses 71a and 75a) or more apart. However, more closely spaced pulses (pulses 77 and 79) still result in an output indicating that only the first pulse (pulse 77a) was detected.
Finally, as shown in FIG. 6, a delay line (half cell delay 81) is needed in the clock recovery circuit. In known variable-power, multiple gate-type delay lines, pulses passing through the delay line may become distorted or even disappear or collapse at low power operating levels or with long delays prior to reaching the delay line output. This occurs because the one-shot pulse conditioning circuitry generally used as the front end of the delay line produces pulses which are too narrow, under certain conditions, for proper delay line functioning. The one-shot circuitry also has the backlash clear limitation on high-frequency operation previously discussed and relative to the data latch and gated clock. A known delay circuit is shown in FIG. 10 and comprises flip-flop 101 and delay elements 103.
The need thus exists for a fast data synchronizing latch, a fast clock gate and a high frequency delay line which can improve the performance of known receiver systems.